1. Field of the Invention
The present invention relates to an apparatus which performs a geometrical operation, such as coordinate transformation, luminance calculation, or a clipping operation, at a high speed in a three-dimensional computer graphic display system.
2. Description of the Prior Art
[Prior Art 1]
FIG. 24 illustrates a three-dimensional (3-D) image generation apparatus disclosed in JP Laid-Open No. Sho 63-86079. This apparatus employs a conventional parallel processor arrangement in which a large number of 3-D vector operations and matrix operations are performed for 3-D graphic image generation at a high speed through parallel execution. FIG. 24 shows the following components: an interface IF between the device and a system bus 10; data memories DBMs1-4 for storing data regarding object form and parameters to be used for image generation; floating processing units FPUs1-3; an arithmetic logic unit FALU; a high speed data bus 20 for connecting the DBMs1-4, the FPUs1-3, and the unit FALU; a data collector DC for collecting image data generated by the processing units, so as to write them into a display memory; a program memory WCS for storing an instruction for controlling respective processing units, memories, and logical circuits; a sequencer SEQ for reading out an instruction from the WCS; and an address generator ADG for generating a physical address for the DBM based on a memory address designation instruction among all the instructions read out by the SEQ from the WCS.
FIG. 25 is a detailed representation showing an example combining the FPUs1-3 and the FALU in FIG. 24. FIG. 25 includes the following components: floating point processors FPPs1-4; an arithmetic logic unit ALU; a multiplexer MPX for selecting one from a plurality of data; registers REGs1-4 for storing operation data; and a reference table LUT for storing parameters for computing various functions, such as roots, trigonometric functions etc., at a high speed. As shown in the drawing, the respective FPPs are connected to one another via MPXs such that an output of one FPP can become an input of the other FPPs. Such a connection of four individually operative FPPs1-4 will allow parallel execution of four separate operations.
FIG. 26 shows steps of a matrix calculation for coordinate transformation, using parallel processors shown in FIG. 25. The expression (1) (described later) comprises matrix components T11, T12, T13, T14, T21, T22, T23, T24, T31, T32, T33, T34, T41, T42, T43, and T44. When it is assumed that data on the first, second, third and fourth four components above are pre-stored in FPP1, FPP2, FPP3, and FPP4, respectively, solving the expression (1) requires sixteen multiplications and twelve additions to be conducted because three additions per line must be conducted for four lines. However, with the use of these parallel processors, the expression (1) can be solved through twelve steps by the FPPs1-4. Nevertheless, it is further desirable if the operation is achieved at a higher speed. ##EQU1##
In this system, although the four parallel processors can operate simultaneously in coordinate transformation, some processors are left idle in some steps, as shown in FIG. 26. For 3-D graphic processing in which a large amount of computation is conducted on a real time basis, it is necessary to enhance the parallel extent of the parallel operations of the processors so as to reduce operational time.
[Prior Art 2]
FIG. 27 is a block diagram showing another prior art, or a sequence control apparatus disclosed in JP Laid-Open No. Sho 64-64034. This prior art apparatus includes sequence circuit hardware which can judge whether or not input information has a particular pattern. FIG. 27 includes the following components: flip flops 2701-1 to 2701-N for holding N bit data, each bit indicating each of N input conditions; an input data generation circuit 2702 for generating N-bit parallel data, using the N outputs of the flip flops 2701-1 to 2701-N; an instruction register 2704-1 for storing an instruction code; a comparison circuit 2703 for comparing the N-bit data from the input data generation circuit 2702 and N-bit data held in the second field (2704-1a) of the instruction register 2704-1, so as to output a matching signal when these data match; a decoder 2704-2 for decoding a condition branch instruction held in the first field of the instruction register 2704-1, so as to output an execution signal; a logical AND circuit 2705 for outputting a logical AND of the matching signal from the comparison circuit 2703 and the execution signal from the decoder 2704-2; branch destination selection circuit 2706 for outputting a branch destination of the condition branch instruction, when receiving a signal from the logical AND circuit 2705; and a program counter 2704-3 for holding the branch destination address when receiving a signal from the branch destination selection circuit 2706.
The operation of this sequence circuit will now be described. When it is assumed that N is eight, the flip flops 2701-1 to 2701-8 hold 8-bit input information, so that the input data generation circuit 2702 generates 8 bit data, based on this information. Provided that the second field of the instruction register 2704-1 contains data "00000011," the comparison circuit 2703 outputs a matching signal when data held in the flip flops 2701-1 to 2701-8 is "00000011." Meanwhile, a decoder 2704-2 decodes an instruction code of a condition branch instruction held in the first field of the instruction registers 2704-01, and outputs decoded data as an execution signal. The logical AND circuit 2705 computes a logical AND of the matching and execution signals, and outputs the result as an output signal. Based on this output signal, the branch destination selection circuit 2706 outputs a branch destination address held in the third field of the instruction register 2704-1, as a branch destination signal, which corresponds to a start address of a certain operation. The program counter 2704-3 holds the address output by the branch destination selection circuit 2706, and the system starts execution of a program at the address held in the program counter 2704-3.
In the branch sequence of this prior art, the operational process is branched only when a bit pattern matches a predetermined single branch condition. Thus, in the case of a plurality of branch conditions and bit patterns, it is necessary to compare respective patterns with every branch condition, which impedes a high speed branch operation.
[Prior Art 3]
A third prior art is described referring to FIG. 28, which relates to a multicast transmission for use in a multi-processor arrangement disclosed in JP Laid-Open No. Hei 3-1264. This drawing includes a main processor 2801 and I/O processors 2802, each operable independently. In this arrangement, when one of the I/O processors 2802 issues address data into a bus, all the other I/O processors 2802 individually monitor the data to see whether the data is addressed thereto, and reads the necessary data. In this method, a multicast transmission is performed by sending data from one source, which addresses more than two destinations.
Generally speaking, in a conventional clipping operation, a clip code generation circuit generates clip codes for plates in the X, Y, and Z directions one by one, to execute a clip judgment of a polygon. As a result, clip judgement takes time to complete, which hinders high speed image drawing.
In this prior art, the respective parallel processors must detect whether data is addressed to themselves, which makes the hardware rather complicated. Further, when one processor transmits data to all the other processors in a conventional SIMD format parallel processor structure, destination processors must be designated one by one, which takes a long transmission time.